Chip design fo submicron VLSI: cmos layout and simulation / by John P. Uyemura
By: Uyemura ,John P.
Material type:
TextPublisher: New Delhi: Cengage Learning, 2006Description: xvi,411p.: ill.,tables; 24cm.ISBN: 9788131501955:.Subject(s): METALOXIDICE CONDUCTORDDC classification: 621.395
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Central Library Library Annex (Ground Floor) | 621.395 UYE/C (Browse shelf) | Available | 117292 | |
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Books
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Central Library Library Annex (Ground Floor) | 621.395 UYE/C (Browse shelf) | Available | 117291 |
Browsing Central Library Shelves , Shelving location: Library Annex (Ground Floor) Close shelf browser
| 621.395 TAU/F Fundamentals of modern VLSI devices / | 621.395 TAU/F Fundamentals of modern VLSI devices / | 621.395 TER/O OP AMPS : | 621.395 UYE/C Chip design fo submicron VLSI: | 621.395 UYE/C Chip design fo submicron VLSI: | 621.395 UYE/I Introduction to VLSI circuits and systems / | 621.395 WES/C CMOS VLSI design : |
Includes index and appendix.
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