Central Library , Vidyasagar University

Your cart is empty.

Online Public Access Catalogue (OPAC)
Central Library - Vidyasagar University

“Education does not only mean learning, reading, writing, and arithmetic,

it should provide a comprehensive knowledge”

-Ishwarchandra Vidyasagar


Yalamanchili, Sudhakar.

Introductory VHDL : from simulation to synthesis / by Sudhakar Yalamanchili. - / . - Delhi : Pearson education , 2003. - xix,401p. : illus.,figs.,tables ; 24cm CD .

Includes Bibliographical references & index

8178085585 Rs. 299.00

VHDL(COMPUTER HARDWARE DESCRIPTION LANGUAGE

621.392 / YAL/I

Powered by Koha