000 00780cam a2200277ua 4500
001 31318
005 20171214164729.0
007 ta
008 091117s2007 Ne a g b000 u eng u
020 _cRS750.00 (Hb)
040 _aMAIN
041 1 _aeng
_hNULL
044 _aNe
082 1 4 _a621.395
_bMAH/T
100 1 _aMaheshwari, Naresh.
245 1 0 _aTiming analysis and optimization of sequential circuits /
_cby Naresh Maheshwari and Sachin S.Sapatnekar.
250 _a /
_b.
260 _aNewDelhi :
_bSpringer (India) ,
_c2007.
300 _a190p. :
_bCalculus ;
_c22cm
_e1 CD .
365 _aRS750.00
504 _aIncludes index and reference
653 0 _aCOMPUTER ENGINEERING
700 1 _aSapatnekar, Sachin S .
942 _cBK
999 _c30996
_d30996